KUAI-EXACT: a new approach for multi-valued logic minimization in VLSI synthesis

A new logic minimizer designed to generate the exact minimum solutions for multivalued input logic expressions is presented. The advantage of this minimizer is that it generates as few prime implicants as possible. A new algorithm is presented for directly generating essential prime implicants in a time close to that for generating a prime implicant by the ESPRESSO-MV expansion process. The authors discuss how to generate the secondary essential prime implicants in order to avoid setting up a covering table, and they present the corresponding algorithms for noncyclic functions. They also discuss the case in which a covering table should be created for obtaining an exact minimum solution and consider how to use the parallel processing techniques for the best speedup