The influence of SiC/SiO2 interface morphology on the electrical characteristics of SiC MOS structures

The effect of roughness at the SiC/SiO₂ interface on electrical properties of 4H-SiC MOS devices has been investigated. Variations in surface roughness were generated by annealing 4H-SiC samples at high temperatures (1550°C-1650°C) with or without a graphitic cap layer. Subsequently, gate oxides were grown on these surfaces for n-type MOS capacitors and n-channel MOSFETs were fabricated. Although the interfaces demonstrated significantly different surface morphology, interface state density (D_it) measured on the capacitors were almost identical. This was reflected in the MOSFET characteristics where, to first order, no obvious difference in field-effect mobility was observed. This result verifies that long range roughness (in the micron scale) does not affect mobility of channel electrons where the mean free path is of the order of a ~ 1 nm due to the low inversion layer mobility.