Digital VLSI architectures for neural networks

Author

Kung, S.Y. ; Hwang, J.N.

Author_Institution

Dept. of Electr. Eng., Princeton Univ., NJ, USA

fYear

1989

Firstpage

445

Abstract

A generic iterative model is proposed for a wide variety of artificial neural networks (ANNs): single-layer feedback networks, multilayer feedforward networks, hierarchical competitive networks, and some probabilistic models. A unified formulation is provided for the retrieving and learning phases of most ANNs. On the basis of the formulation, a programmable ring systolic array is developed. The architecture maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. It can be adopted as a basic structure for a universal neurocomputer architecture

Keywords

VLSI; cellular arrays; learning systems; neural nets; parallel architectures; pipeline processing; ANNs; artificial neural networks; generic iterative model; hierarchical competitive networks; learning phases; multilayer feedforward networks; neural networks; pipelined computing; probabilistic models; programmable ring systolic array; single-layer feedback networks; universal neurocomputer architecture; Artificial neural networks; Computer architecture; Feedforward neural networks; Multi-layer neural network; Neural networks; Neurofeedback; Neurons; Nonlinear equations; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100386

Filename

100386