Design and implementation of a shared memory switch fabric

Broadband networks satisfy the need to carry integrated traffic involving different types of information such as voice, video and data. Furthermore different services with multiple requirements need specific capabilities to be provided and guaranteed by broadband networks. The architecture of next generation networks has an important effect on changing the broadband networks and providing these capabilities. On the other hand, the architecture of broad band networks is highly affected by high speed switches. In fact, high speed switches are the target technology to achieve the required capabilities. The performance demands and changes in IC and VLSI technology have led to emergence of different types of switch architectures. This paper, proposes the architectural details of a scalable, high speed shared memory switch fabric which is operating at 20Gbps. The presented architecture is implemented using FPGA technology based on Xilinx´s Virtex 4 family. The design presents a scalable architecture by implementing dynamic address allocation and efficient internal timing management. In our proposed architecture, we also consider some of VLSI design issues to make it more appropriate for further chip designs.