Wafer scale architecture for an FFT processor

A description is given of research on a WSI FFT processor. Attention is focused on the design methodology, architecture, and sparing strategy and restructuring. The basic cells utilized are the MSA and the coefficient ROM. The wafer thus has only two types of cell, making the algorithm highly suitable for restructable wafer-scale integration (WSI) design. The restructuring algorithm is discussed briefly, and the tradeoffs between cell redundancy, wafer-area utilization, and effective yield are evaluated. Indeed, interest in WSI arises from expectations of higher speed, better reliability, and significant improvement in the circuit density. This FFT wafer represents the first of several envisioned in large-scale signal processing and computing under a DARPA microelectronics project in progress