A modulo bit-level systolic compiler

The production of advanced software to automate the VLSI design of very-high-speed signal processing integrated circuits is discussed. The circuits are based on a class of bit-level systolic arrays implemented with a single generic cell. The generic cell computes over finite rings and offers fixed coefficient multiplication with the same complexity measure as addition. The resulting architecture is composed of linear arrays of systolic, steerable dynamic ROMs. Because of the class restriction, efficient designs can be produced, with all design criteria met. The front-end of the system is a design tool that will act as an assistant to a designer who is experienced with signal processing systems but possibly not familiar with VLSI design technology. The back-end is a system for configuring standardized bit-level systolic cells. The front-end system consists of a knowledge-based system and a transformer. This system interfaces to a conventional VLSI design and verification package, with the output in a form suitable for direct use by the silicon foundry