DocumentCode
1625254
Title
STA: a tool for systolic array reasoning
Author
Ling, Nom ; Bayoumi, Magdy A.
Author_Institution
Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA
fYear
1989
Firstpage
461
Abstract
A concise introduction to a novel formalism developed for systolic array reasoning is presented. This new formalism is called systolic temporal arithmetic (STA). The motivation for such a development, its syntax, and some of the constructs and rules involved are briefly presented. Its applications to formal specification, formal verification, simulation, fault diagnosis, and test generation for systolic arrays are briefly discussed
Keywords
cellular arrays; digital arithmetic; formal languages; formal specification; logic design; parallel architectures; fault diagnosis; formal specification; formal verification; formalism; syntax; systolic array reasoning; systolic temporal arithmetic; test generation; Architecture description languages; Arithmetic; Circuit faults; Digital systems; Fault diagnosis; Formal specifications; Formal verification; Software tools; Systolic arrays; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location
Portland, OR
Type
conf
DOI
10.1109/ISCAS.1989.100390
Filename
100390
Link To Document