DocumentCode
1625594
Title
Half micron BiCMOS device and process modeling
Author
Borucki, L. ; Zirkle, T. ; Kirchgessner, J. ; Drennan, P.
Author_Institution
Motorola, Inc., Chandler, AZ, USA
fYear
1993
Firstpage
97
Lastpage
103
Abstract
Key process and device modeling issues are described that were addressed during development and optimization of a high performance NPN transistor built in a 0.5 μm BiCMOS technology for digital and mixed signal applications. Process issues included the deconvolution of shallow SIMS emitter profiles to obtain a more accurate picture of the underlying intrinsic device, detailed modeling of grain growth and diffusion in the dual polysilicon structure, and modeling of lateral diffusion of the link base. Extensive RSM device modeling was used to simulate trends in device characteristics resulting from variations in device structure. This work resulted in a device with improved overall performance
Keywords
BiCMOS integrated circuits; 0.5 micron; RSM device modeling; RTA; Si; deconvolution; diffusion; dual polysilicon structure; grain growth; half micron BiCMOS device modeling; high performance NPN transistor; lateral diffusion; optimization; process modeling; shallow SIMS emitter profiles; BiCMOS integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCOMS Circuits and Technology Meeting, 1993., Proceedings of the 1993
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-1316-X
Type
conf
DOI
10.1109/BIPOL.1993.617477
Filename
617477
Link To Document