Design of an LVCMOS high resolution frequency synthesizer

Author

Lobato-Lopez, F. ; Solis-Bustos, S. ; Sucar, H.R.

Author_Institution

Motorola Semicond. Products Sector, Mexico Center for Semicond. Technol., Puebla, Mexico

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

This work presents the design and implementation of a high frequency high resolution clock synthesizer. A phased-locked-loop (PLL) with internal feedback is the core of the synthesizer. The operating frequency range of the PLL oscillator is 1 GHz to 2 GHz. High resolution is achieved by a wide range programmable feedback divider from 1 to 1024 divide factors in steps of 1. A programmable current mode charge pump is designed to manage the wide range feedback divider. Circuit simulation results demonstrate design feasibility. The design was implemented on a 0.18 μm low voltage CMOS (LVCMOS) technology.

Keywords

CMOS integrated circuits; circuit feedback; circuit simulation; current-mode circuits; frequency synthesizers; integrated circuit design; low-power electronics; phase locked loops; programmable circuits; signal resolution; 0.18 micron; 1 to 2 GHz; LVCMOS frequency synthesizer design; PLL internal feedback; PLL oscillator; circuit simulation; design feasibility; divide factors; frequency synthesizer resolution; low voltage CMOS technology; operating frequency range; phased-locked loop core; programmable current mode charge pump; programmable feedback divider; CMOS technology; Charge pumps; Clocks; Feedback; Frequency conversion; Frequency synthesizers; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on

Print_ISBN

0-7803-7380-4

Type

conf

DOI

10.1109/ICCDCS.2002.1004005

Filename

1004005