Positioning test-benches and test-programs in interaction-oriented system-on-chip verification

In simulation-based system-on-chip (SoC) verification, in addition to the testbench (TB) - the basic facility for stimulation and observation, software native to the SoC also plays a part in interacting with the SoC. This software is referred to as the test-program (TP). However, the relationship between the TB, the TP and the SoC is not always intuitive and can cause conceptual confusion. This paper discusses this confusion and shows how to address it by positioning the TB and the TP naturally in the verification framework.