Comparison of NMOS and CMOS TFT inverters fabricated by LPCVD and SPC techniques at low temperature (<600°C)

Author

Gautier, Gaël ; Viana, Carlos Eduardo ; Crand, Samuel ; Rogel, Regis ; Morimoto, N.I. ; Bonnaud, Olivier

Author_Institution

GMV, Rennes I Univ., France

fYear

2002

fDate

6/24/1905 12:00:00 AM

Abstract

After several experimental studies on improvement of the electrical performances of N-type polysilicon thin-film transistors (NMOS-TFT) fabricated by LPCVD (Low Pressure Chemical Vapor Deposition) and SPC (Solid Phase Crystallization) techniques at low temperature, it was necessary to implement a process to design a complementary TFT cell technology (CMOS-like TFT). This elementary cell is useful indeed essential to design efficient digital circuits. This paper describes the process developed and presents a comparison between two inverters: NMOS-inverter based on the use of two NMOS-TFTs and a CMOS-like TFT inverter. This work has allowed to validate the process and to quantify the improvement of the electrical characteristics such as noise margins, gain and output voltage amplitude.

Keywords

MOSFET; chemical vapour deposition; crystallisation; logic gates; thin film transistors; 600 C; CMOS TFT inverter; N-type polysilicon thin film transistor; NMOS TFT inverter; digital circuit; electrical characteristics; low pressure chemical vapor deposition; low temperature fabrication; solid phase crystallization; CMOS technology; Chemical technology; Chemical vapor deposition; Crystallization; Inverters; MOS devices; Process design; Solids; Temperature; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on

Print_ISBN

0-7803-7380-4

Type

conf

DOI

10.1109/ICCDCS.2002.1004028

Filename

1004028