Performance enhancement in vertical sub-100 nm nMOSFETs with graded doped channels

Graded channel doping in vertical sub-100 nm nMOSFETs was investigated in this study. Conventional single step ion implantation was used to form the asymmetric, graded doping profile in the channel. No large-angle-tilt implant was needed. The device fabrication was compatible with conventional Si CMOS technology. In a graded doped channel, with the higher doping level in the source end of the channel, drain induced barrier lowering and off-state leakage current were reduced significantly. In addition, lower longitudinal electric field in the drain end can be achieved without lightly doped drain (LDD), and hot carrier effects were reduced substantially with this device.