Optimum design of device/circuit cooperative schemes for ultra-low power applications

The miniaturization of MOS transistors has been the only guideline for device design for high performance VLSIs. Approaching to the fundamental scaling limit, various critical issues have arisen in sub-100 nm CMOS devices such as the increase in power dissipation and device degradation due to short channel effects. In order to solve these problems and go into the deep sub-100 nm regime, new device design guidelines should be developed. In this paper, cooperation between device and circuit is proposed for ultra-low power applications. The optimum design in low power circuit schemes is discussed from the device point of view, especially for the suppression of stand-by power.