Testing for coupled cells in random-access memories

Author

Savir, J. ; McAnney, W.H. ; Vecchio, S.R.

Author_Institution

IBM, Poughkeepsie, NY, USA

fYear

1989

Firstpage

439

Lastpage

451

Abstract

Five test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-b random-access memory. In all five test strategies the data-in line is randomly driven. Three of five strategies use random selection of both the address lines and the read/write control. The other two strategies sequentially cycle through the address space with deterministic setting of the read/write control. The relative merit of these five strategies is measured by the average number of accesses per address needed to meet a standard test quality level. It is concluded that ETWO (explicit memory test with word operations) offers the best performance and is quite easy to implement

Keywords

failure analysis; fault location; integrated circuit testing; integrated memory circuits; logic testing; random processes; random-access storage; address lines; coupled cells; cycle operations; data-in line; deterministic setting; explicit memory test; fault location; memory unload; random selection; random-access memories; read/write control; segmented random memory test; sequential cycling; word operations; Analytical models; Data systems; Decoding; Fault detection; Measurement standards; Random access memory; Read-write memory; System testing; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82327

Filename

82327