DocumentCode
1626920
Title
CMOS downsizing and high-K gate insulator technology
Author
Iwai, Hiroshi ; Ohmi, Shun´ichiro
Author_Institution
Interdisciplinary Graduate Sch. of Sci. & Eng., Tokyo Inst. of Technol., Yokohama, Japan
fYear
2002
fDate
6/24/1905 12:00:00 AM
Abstract
Downscaling of MOSFETs is the driving force of the development of new generation CMOS ULSIs. Now, gate lengths of the transistors have reached sub-100 nm in production and 15 nm in research. However, many difficulties are expected to further downsizing of the device dimensions. The biggest difficulty at this moment is the thinning of the gate oxide. In this paper, problems the downsizing and expected solutions in particular those for the gate oxide thinning for miniaturized CMOS ULSI devices are explained.
Keywords
CMOS integrated circuits; MOSFET; ULSI; integrated circuit technology; 100 nm; 15 nm; CMOS ULSI device; MOSFET downsizing; gate oxide thinning; high-K gate insulator technology; CMOS technology; Dielectrics and electrical insulation; High K dielectric materials; High-K gate dielectrics; Impurities; Large scale integration; MOSFETs; Substrates; Threshold voltage; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, 2002. Proceedings of the Fourth IEEE International Caracas Conference on
Print_ISBN
0-7803-7380-4
Type
conf
DOI
10.1109/ICCDCS.2002.1004072
Filename
1004072
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