Title :
Two zero and two pole active compensation replaces a charge pump in PLLs
Author :
Goldman, Stanley J.
Author_Institution :
Texas Instrum., Dallas, TX
Abstract :
A 2 zero and 2 pole compensation circuit with an operational amplifier replacing a charge pump in a PLL has been fabricated in an 0.065 mum gate length CMOS technology. It achieves state of art performance with 1 mW low power dissipation at 240 MHz output frequency and a small 0.06 mm2 area. The circuit has a wide output frequency range of 12-600 MHz with a low jitter measurement of 80 ps peak to peak.
Keywords :
active networks; jitter; operational amplifiers; phase locked loops; CMOS technology; PLL; charge pump; compensation circuit; frequency 12 MHz to 600 MHz; jitter; operational amplifier; output frequency; power 1 mW; power dissipation; size 0.065 micron; Art; CMOS technology; Charge pumps; Circuits; Frequency; Jitter; Operational amplifiers; Phase locked loops; Poles and zeros; Power dissipation; Bode diagrams; compensation; control systems; feedback circuits; frequency synthesizers; phase locked loops; poles and zeros;
Conference_Titel :
Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software, 2008 IEEE Dallas
Conference_Location :
Dallas, TX
Print_ISBN :
978-1-4244-2955-4
Electronic_ISBN :
978-1-4244-2956-1
DOI :
10.1109/DCAS.2008.4695914
