III–V FET channel designs for high current densities and thin inversion layers

III-V FETs are being developed for potential application in 0.3-3 THz systems and VLSI. To increase bandwidth, we must increase the drive current I_d = qn_sv_injW_g per unit gate width W_g, requiring both high sheet carrier concentrations n_s and high injection velocities v_inj. Present III-V NFETs restrict control region transport to the single isotropic Γ band minimum. As the gate dielectric is thinned, I_d becomes limited by the effective mass m*, and is only increased by using materials with increased m* and hence increased transit times. The deep wavefunction also makes Γ-valley transport in low-m* materials unsuitable for <; 22-nm gate length (L_g) FETs. Yet, the L-valleys in many III-V materials have very low transverse m_i and very high longitudinal mass m_i. L-valley bound state energies depend upon orientation, and the directions of confinement, growth, and transport can be chosen to selectively populate valleys having low mass in the transport direction. The high perpendicular mass permits placement of multiple quantum wells spaced by a few nm, or population of multiple states of a thicker well spaced by ~10-100 meV. Using combinations of Γ and L valleys, n_s can be increased, m* kept low, and vertical confinement improved, key requirements for <;20-nm L_g III-V FETs.