Title :
Symbolic test generation for hierarchically modeled digital systems
Author :
Anirudhan, P.N. ; Menon, P.R.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
The authors present a symbolic test generation algorithm which uses a hierarchical model of the data path and a finite state model of the control section of the system under test. The data path may contain sequential modules, as well as synchronous feedback loops. The stable table of the control section can be used by the test generation algorithm to generate test even in complex sequential modes of operation of the system. The symbolic approach presented is applicable with a top-down, as well as a bottom-up, approach to hierarchical test generation. With a top-down approach, symbolic constraints derived at a higher level are used in deriving module tests, thereby guaranteeing that the tests will be applicable in the environment in which the module is used. If a bottom-up approach is used, tests for any module in its operating environment are obtained by combining symbolic tests and module tests
Keywords :
VLSI; automatic testing; digital integrated circuits; electronic engineering computing; feedback; hierarchical systems; integrated circuit testing; logic testing; modules; VLSI; bottom-up; data path; finite state model; hierarchically modeled digital systems; sequential modules; symbolic constraints; symbolic test generation algorithm; synchronous feedback loops; top-down; Circuit faults; Circuit testing; Control systems; Digital systems; Feedback loop; Instruments; Integrated circuit interconnections; Sequential analysis; System testing; Very large scale integration;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82329