Bottom up approach to enhance top level SoC verification

SoCs today rely heavily on behavioral models of analog circuits for Top Level Verification. The minimum modeling requirement is to model the functional behavior of the circuit. A lot of ongoing work is also focused on modeling analog circuits to predict the system performance of the SoC. This paper presents a methodology to enhance the quality of SoC verification by using a bottom up approach to verify the equivalence of building blocks and then work at higher levels to increase coverage. It is shown that this methodology can be used to verify functional and performance equivalence of behavioral models.