A 6-bit 300-MS/s 2.7mW ADC based on linear voltage controlled delay line

Author

Zhang, Chaoming ; Abraham, Jacob A. ; Hassibi, Arjang

Author_Institution

Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX

fYear

2008

Firstpage

1

Lastpage

4

Abstract

This paper describes a novel ADC architecture based on time domain processing. By using a voltage controlled delay line, a linear transfer function of the input dependent delay is formed. The time delay difference is then compared to a reference to generate a digital code for the input. We have designed a 300-MS/s 6 bit ADC using this architecture in a 0.13 m standard digital CMOS. The simulation results show 36.6 dB SNR, 34.1 dB SNDR for 99 MHz input, DNL<0.2LSB, and INL<0.5LSB. Overall chip power is 2.7 mW with a 1.2 V power supply.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; delay lines; digital integrated circuits; voltage control; ADC; chip power; delay line; digital code; frequency 99 MHz; linear transfer function; linear voltage control; power 2.7 mW; standard digital CMOS; time delay difference; voltage 1.2 V; Circuits; Delay effects; Delay lines; Dynamic range; Dynamic voltage scaling; Frequency; Linearity; Timing; Voltage control; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems Workshop: System-on-Chip - Design, Applications, Integration, and Software, 2008 IEEE Dallas

Conference_Location

Dallas, TX

Print_ISBN

978-1-4244-2955-4

Electronic_ISBN

978-1-4244-2956-1

Type

conf

DOI

10.1109/DCAS.2008.4695930

Filename

4695930