Title :
Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design
Author :
Kranti, A. ; Rashmi ; Burignat, S. ; Raskin, J.P. ; Armstrong, G.A.
Author_Institution :
Semicond. & Nanotechnol. Group, Queen´´s Univ. Belfast, Belfast, UK
Abstract :
In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (AVO) and cut-off frequency (fT) along with a broader analog `sweet spot´ in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (~10 ¿A/¿m) but extend up to 100 ¿A/¿m which corresponds to optimum AVO and fT performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in fT along with a 2 fold enhancement in AVO. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.
Keywords :
MOSFET; nanoelectronics; silicon-on-insulator; UTBB SOI MOSFET; analog/RF performance metrics; cut-off frequency; higher voltage gain; nanoscale MOSFET; nonclassical gate-source/drain underlap channel design; source/drain channel architecture; ultra thin body box; CMOS technology; Doping profiles; Integrated circuit technology; Low voltage; MOSFETs; Measurement; Nanotechnology; Performance analysis; Radio frequency; Semiconductor process modeling; Analog/RF metrics; Cut-off frequency; Nanoscale; SOI MOSFETs; Underlap channel; Voltage gain;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on
Conference_Location :
New Orleans, LA
Print_ISBN :
978-1-4244-5456-3
DOI :
10.1109/SMIC.2010.5422943
