Title :
Statistical modelling of Idd testing efficiency of analogue integrated circuits
Author :
MUSIL, Vladislav
Author_Institution :
Dept. of Microelectron., Tech. Univ. of Brno, Czech Republic
Abstract :
The paper describes a new implementation of a testing-algorithm model for analogue circuits. It is based on the possibilities of HSPICE and MATLAB to manage a whole test simulation including the simulation of faulty or fault free circuits as well as their post-processing. The approach takes into account the tolerance deviations of the parameters. Both low-level and high-level modelling are assumed. The aim of this project is to model test techniques using supply current monitoring in order to classify their effectiveness in terms of fault coverage
Keywords :
SPICE; analogue integrated circuits; circuit analysis computing; integrated circuit testing; mixed analogue-digital integrated circuits; statistical analysis; tolerance analysis; HSPICE; MATLAB; analogue integrated circuits; current testing efficiency; fault coverage; fault free circuits; faulty circuits; high-level modelling; low-level modelling; mixed-signal integrated circuits; parameter tolerance deviations; postprocessing; statistical modelling; supply current monitoring; test simulation; testing-algorithm model; Analog integrated circuits; Circuit faults; Circuit testing; Computational modeling; Current supplies; Integrated circuit modeling; Integrated circuit testing; Mathematical model; Monitoring; Voltage;
Conference_Titel :
Signals, Systems, and Electronics, 1995. ISSSE '95, Proceedings., 1995 URSI International Symposium on
Conference_Location :
San Francisco
Print_ISBN :
0-7803-2516-8
DOI :
10.1109/ISSSE.1995.498019
