DocumentCode
1627744
Title
A 1.9V 25GHz SiGe static frequency dividers with clock-sharing topology
Author
Cai, Weiran ; Ellinger, Frank ; Carls, Jörg
Author_Institution
Tech. Univ. Dresden, Dresden, Germany
fYear
2010
Firstpage
247
Lastpage
250
Abstract
A novel low-voltage, high-speed static divider topology using shared clock-transistors is proposed. The divide-by-2 is implemented in 0.18 ¿m 60 GHz-fT SiGe BiCMOS technology. At 1.9 V × 9 mA supply power of the divider core, an operation frequency of up to 25 GHz was measured. Compared to the conventional D flip-flop architecture, at similar speed, a reduction of 34% in supply power is enabled.
Keywords
BiCMOS integrated circuits; Ge-Si alloys; clocks; flip-flops; frequency dividers; network topology; transistor circuits; BiCMOS technology; D flip-flop architecture; clock-sharing topology; frequency 25 GHz; low-voltagestatic divider topology; shared clock-transistors; size 0.18 mum; static frequency dividers; voltage 1.9 V; BiCMOS integrated circuits; Clocks; Flip-flops; Frequency conversion; Frequency measurement; Germanium silicon alloys; Power measurement; Power supplies; Silicon germanium; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on
Conference_Location
New Orleans, LA
Print_ISBN
978-1-4244-5456-3
Type
conf
DOI
10.1109/SMIC.2010.5422950
Filename
5422950
Link To Document