Simulating communication I/O bottleneck in the partition of VLSI array processors

A quantitative analysis and simulation of the physical decomposition of VLSI array processors in terms of an I/O bandwidth problem is presented. Such an I/O problem has been a major issue in communications among parallel processors. The simulation is done by relating the number of partitioned processing elements (PEs) and points per chip to an I/O bottlenecking index. This I/O bottlenecking index, BI, provides an indication of the occurrence of an I/O bottleneck of operands during chipwise partitioning of an array structure. By examining BI and the number of pinouts allowed per modularized array or chip, one can evaluate the tradeoff of various physical partitions to the tessellated arrays of PEs versus the I/O pin limitation