Title :
Optimized latch-up design of a high voltage nLDMOSFET
Author :
Chen, Shen-Li ; Wu, Tzung-Shian ; Chen, Hung-Wei ; Shih, Chun-Hsing ; Chen, Po-Ying
Author_Institution :
Dept. of Electron. Eng., Nat. United Univ., Miaoli, Taiwan
Abstract :
Both drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic nLDMOS are presented in this work. It is a novel method to reduce trigger voltage (Vt1) and to increase holding voltage (Vh). These efforts will be very suitable for the HV power management IC applications. Meanwhile, in this work, we will discuss trigger voltage and holding voltage distributions of these novel HV nLDMOS devices.
Keywords :
MOS integrated circuits; MOSFET; HV power management IC applications; drain-side engineering; high voltage nLDMOSFET; holding voltage distributions; optimized latch-up design; source-side engineering; trigger voltage distributions; Electrostatic discharge; Implants; Integrated circuit reliability; Junctions; Noise; Resistance; Voltage control;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667294
