Energy-efficient imprecise reconfigurable computing through probabilistic domain transformation

Many DSP applications naturally possess so-called “inherent error resilience”, meaning certain degrees of computational errors would not noticeably impair their eventual quality of results. Such a phenomenon offers an interesting opportunity to significantly improve the overall energy efficiency of these DSP applications at the cost of minute degradations in computing accuracy. This work presents a probabilistic-based methodology to perform high-performance DSP applications while achieving low power consumption. Deviating from all published approximate computing methods, our solution leverages a fundamental probability principle to implement a reconfigurable finite impulse response FIR digital filter specifically designed for FPGA-based image and video processors. Our method is trading off performance efficiency and power consumption against accuracy of the output results. To validate this proposed probabilistic architecture for discrete FIR filter, We have developed a 16-tap FIR filter with Virtex 5 FPGA devices (XC5VSX95T-1FF1136). Our prototype of probabilistic-based reconfigurable FIR filter consumes 9 times less power than multiplier-based FIR filter and dissipates 43.13 μJ in dynamic energy consumption to perform filtering on a (256×256) pixel image. We believe that this new architecture can be exploited in all the real-time applications in which energy-efficient FIR filters are required and it can be realized with many other FPGA device families.