Self-aligned graphene-on-SiC and graphene-on-Si MOSFETs on 75 mm wafers

In this talk, we present recent progress in epitaxial graphene n-MOSFETs and p-MOSFETs on both SiC and Si substrates for graphene-on-SiC and graphene-on-Si technologies. Both graphene MOSFETs were fabricated in a self-aligned manner on 75 mm wafers and exhibited gate-controlled ambipolar characteristics. For the graphene MOSFETs on SiC substrates, the graphene was grown by Si-sublimation of Si-face 6H-SiC substrates in a commercial Aixtron VP508 epitaxial reactor. For the graphene MOSFETs on Si substrates, the graphene was synthesized by graphitizing a thin 3C-SiC layer grown on float-zone Si (111) substrates using a halogen process. Figure 1 shows sheet resistance maps of 3-inch graphene-on-SiC and graphene-on-Si wafers. Typical Hall mobility ranges from 500 to 2000 cm2/Vs depending on electron carrier density. Both graphene MOSFETs were fabricated with a gate oxide layer and metal gate stack. The gate length was 3 μm. The graphene-on-SiC MOSFETs showed excellent I-V saturation behavior as shown in Figure 2(a). Figure 2(b) shows measured ambipolar behaviors with n-type MOSFET at Vgs = 0 V, while p-type behaviors are observed at Vgs <;-1.5 V. An I_on/I_off ratio of 33 was measured. Figure 2(c) shows measured peak transconductance of 600 mS/mm at V_ds = 3 V. Figure 3 shows the extrinsic field-effect mobility of 6000 cm2/Vs for electron and of 3200 cm2/Vs for hole obtained at an effective electric field of -0.27 MV/cm, approaching Dirac point. The measured graphene field-effect mobility is eight to 10 times higher than that of ITRS Si n-MOSFETs and -80 times higher than that of ultra-thin-body SOI nMOSFETs.