DocumentCode
1628012
Title
Process and device optimization of a 30-GHz fT submicrometer double poly-Si bipolar technology
Author
Yamaguchi, Tad ; Uppili, Sudarsan ; Kawamoto, Galen ; Lee, June ; Simpkins, Shaun
Author_Institution
Tektronix, Inc., Beaverton, OR, USA
fYear
1993
Firstpage
136
Lastpage
139
Abstract
A 30-GHz fT submicrometer double poly-Si bipolar technology has been developed. Performance trade-off characteristics of npn transistors are re-examined as functions of primary process parameters to satisfy the requirements of high-speed analog and analog mixed with digital circuit applications. Schottky diodes, lateral pnp transistors, and laser wafer trimmable precision NiCr resistors by using one additional photo-masking process step. Manufacturability issues such as improvement of C-E leakage currents, RIE process effects on emitter poly-Si to Si interface properties, and planarization of double poly-Si emitter/base structures using a BPSG film reflow process are investigated
Keywords
bipolar analogue integrated circuits; 30 GHz; B2O3-P2O5-SiO2; BF2 implantation; BPSG film reflow; RIE process effects; RTA; Schottky diodes; Si; deep trench isolation; device optimization; double polysilicon bipolar technology; elemental semiconductor; high-speed analog circuits; laser wafer trimmable; lateral pnp transistors; leakage currents; manufacturability; mixed analog-digital circuits; npn transistors; performance tradeoffs; photo-masking; planarization; precision NiCr resistors; process optimization; submicron technology; Bipolar analog integrated circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCOMS Circuits and Technology Meeting, 1993., Proceedings of the 1993
Conference_Location
Minneapolis, MN
Print_ISBN
0-7803-1316-X
Type
conf
DOI
10.1109/BIPOL.1993.617485
Filename
617485
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