Redundancies and don´t cares in sequential logic synthesis

The authors explore the relationships between redundant logic and don´t care conditions in sequential circuits. Stuck-at faults in a sequential circuit may be testable in the combinational sense but may be redundant because they do not alter the terminal behavior of a nonscan sequential machine. These sequential redundancies result in a faulty state transition graph (STG) that is equivalent to the STG of the true machine. The authors present a classification of redundant faults in sequential circuits composed of single or interacting finite-state machines. Don´t care sets can be defined for each class of redundancy, and optimally exploiting these don´t care conditions results in the implicit elimination of any such redundancies in a given circuit. In cascaded and interconnected sequential circuits, sequential don´t cares are required to eliminate redundancies. The authors present preliminary experimental results which indicate that by exploiting these don´t cares medium-sized irredundant sequential circuits can be synthesized with no area overhead and within reasonable CPU times