Title : 
Investigation on the role of hole traps under NBTI stress in PMOS device with plasma-nitrided dielectric oxide
         
        
            Author : 
Liao, Y. ; Ji, X. ; Wu, F. ; Zhu, X. ; Yan, F. ; Shi, Y. ; Zhang, D. ; Guo, Q.
         
        
            Author_Institution : 
Inst. of Electron. Sci. & Eng., Nanjing Univ., Nanjing, China
         
        
        
        
        
            Abstract : 
Negative bias temperature instability (NBTI) recovery for pure-SiO2 and plasma-nitrided oxide (PNO)-based PMOSFET has been investigated at room and below temperature. It is found that the generated hole traps in SiON dielectric under NBTI stress has a broadened energy distribution than that in SiO2 dielectric. This broadened maybe due to nitrogen related traps (K center) In SiON. The traps´ location in SiO2 and SiON are investigated by charge-pumping (CP) technique. In SiON most of Nitrogen-related traps located away from SiON/Si interface. The traps in SiO2 (E´ center) are at SiO2/Si interface. Based on the result of CP, nitrogen related traps located at a distance from SiON/Si interface (γ0=10-5s), we use the inelastic tunneling model to fit the degradation data of NBTI for PNO PMOSFET at 268K and 218K. Simulation results indicate a good agreement with the experimental data. These results show the nitrogen related traps play an important role in hole trapping under NBTI stress.
         
        
            Keywords : 
MOSFET; dielectric materials; elemental semiconductors; hole traps; semiconductor device models; semiconductor device reliability; silicon; silicon compounds; tunnelling; E´ center; K center; NBTI stress; PMOS device reliability; PMOSFET simulation; SiO2-Si; SiON-Si; charge-pumping technique; energy distribution; hole trapping; hole traps; inelastic tunneling model; negative bias temperature instability recovery; nitrogen-related traps; plasma-nitrided dielectric oxide; temperature 218 K; temperature 268 K; temperature 293 K to 298 K; Charge carrier processes; Dielectrics; Nitrogen; Silicon; Stress; Tunneling; Voltage measurement;
         
        
        
        
            Conference_Titel : 
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
         
        
            Conference_Location : 
Shanghai
         
        
            Print_ISBN : 
978-1-4244-5797-7
         
        
        
            DOI : 
10.1109/ICSICT.2010.5667300