Implementation of Systolic RLS Adaptive Array Using FPGA and Its Performance Evaluation

In high-speed mobile radio communication, fast weight adaptation will be required. Recent progress of VLSI technology enables the higher order of parallel processing in matrix computation by using a high density Field Programmable Gate Array (FPGA), thus the computation performance can be improved. There are some well-known optimization techniques to obtain the optimum weights, Recursive Least Squares (RLS) algorithm is known as fast convergence property, but the complexity increases in proportion to the square of the number of array elements. This paper presents FPGA implementation of RLS systolic array processor exploiting parallel pipeline scheme with a developed prototype system in each case of floating-point and fixed-point arithmetic, respectively. The fixed- point implementation is based on hardware-friendly coordinate rotation digital computer (CORDIC) method. The convergence performance of RLS systolic array antenna is compared with conventional RLS algorithm. The convergence speed of RLS systolic array is five times as fast as that of conventional RLS algorithm. Moreover, the circuit scale of the proposed system with fixed-point computation becomes about 1/19 compared with conventional RLS systolic array.