FAST: A framework of accurate SER-estimation at transistor-level for logic circuits

With the development of VLSI technology, logic circuits are becoming more and more vulnerable to soft errors due to particle hits. In order to guide reliable logic circuit design, it is important to develop efficient tools for soft error rate estimation. In this paper, we present a framework FAST for accurate SER estimation in logic circuits. FAST models detailed behaviors of transient pulses in logic circuits at three phases, including SET generation, propagation and capture. Furthermore, FAST uses an accurate transistor-level linear model for estimating the possibility of transient pulse generation. Experimental results indicate that the proposed framework achieves good accuracy compared to the SPICE simulation, while it comes to a higher efficiency than electrical level simulation.