Novel BiST methods for parametric test in wireless transceivers

Author

Webster, D. ; Thiagarajan, G. ; Ramakrishnan, S. ; Gunturi, S. ; Sontakke, A. ; Lie, D.Y.C.

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Tech Univ., Lubbock, TX, USA

fYear

2010

Firstpage

112

Lastpage

115

Abstract

This paper describes RF built-in self test (BiST) techniques to test the performance of a RF CMOS integrated wireless transceiver using on-chip digital resources as both the stimuli and response analyzer. Using a defect-oriented approach, key RF blocks as well as the overall functionality and performance of the device are analyzed using a combination of block level and loopback testing. Using these methods, contributors to error vector magnitude (EVM) such as amplifier gain, phase noise, and linearity performance (IP3) can be estimated and collected to predict the functional performance of a digital radio processor (DRP) for wireless applications.

Keywords

CMOS integrated circuits; amplifiers; built-in self test; circuit testing; phase noise; radiofrequency integrated circuits; transceivers; BiST method; RF CMOS integrated wireless transceiver; RF built-in self test; amplifier gain; block level; defect-oriented approach; digital radio processor; error vector magnitude; key RF block; linearity performance; loopback testing; on-chip digital resources; parametric test; phase noise; response analyzer; stimuli analyzer; Automatic testing; Digital communication; Linearity; Performance analysis; Performance gain; Phase estimation; Phase noise; Radio frequency; Radiofrequency amplifiers; Transceivers; Built-in self-testing (BiST); CMOS integrated circuits; Wireless LAN;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010 Topical Meeting on

Conference_Location

New Orleans, LA

Print_ISBN

978-1-4244-5456-3

Type

conf

DOI

10.1109/SMIC.2010.5422977

Filename

5422977