Graphene nanoribbon Schottky-barrier FETs for end-of-the-roadmap CMOS: Challenges and opportunities

On the ITR.S roadmap, the physical gate length, LG, has been rapidly scaling down, and will reach values below ~ 10nm beyond 2020. The single-gate (SG) extremely thin SOI (ETSOI) MOSFET, the double-gate (DG) FinFET, and the gate-all-around (GAA) Si nanowire (SiNW) MOSFET geometries may facilitate such scaling. Nevertheless, sub-10nm Lα scaling will be a great challenge because of the significant mobility degradation and channel thickness variations in the aforementioned geometries with a few-nanometer body thicknesses as required by electrostatic short-channel considerations. Therefore, new device geometries and technologies are required that could simultaneously maintain the electrostatic integrity and the superior transport properties for sub-lOnm Lα scaling. It has been recently shown that the atomic-thin-body (ATB) geometry can meet the electrostatic requirements for LG <; 10nm. At the ATB limit, carbon electronics based on graphene nanoribbons (GNRs) with tunable band gaps have been widely considered for high-performance digital electronics. Here, ballistic transport of GNR Schottky-barrier (SB) FETs is simulated self-consistently, including both thermionic emission and tunneling. We show the better gate length scalability of GNRs compared to Si MOSFETs, even though significant material related challenges will have to be overcome. Lα scaling below 10nm is mainly limited by direct source-to-drain tunneling and the ambipolar effect in the off-state, which can be suppressed by narrower ribbon widths (of the order ~ 10nm), and larger effective masses obtained from band structure engineering. If a negative metal-graphene SB-height could be achieved, the GNR SB-FET could operate without significant series resistance effects, and deliver high on-current (I_ON ). The performance of the ultimate GNR SB-FETs is comparable to the MOSFET targets of the ITRS roadmap.