Title :
Modeling and analysis of read (RD) disturb in 1T-1STT MTJ memory bits
Author :
Raychowdhury, Arijit ; Somasekhar, Dinesh ; Karnik, Tanay ; De, Vivek K.
Author_Institution :
Circuits Res. Lab., Intel Corp., Hillsboro, OR, USA
Abstract :
The paper presents a RD disturb model study of STT-MTJ memory bits. It shows that high-current short-pulsed RD may cause failure under hammer conditions. Analytical models for such have been developed and validated against numerical simulations.
Keywords :
random-access storage; 1T-1STT MTJ memory bits; hammer conditions; high-current short-pulsed RD disturb model; nonvolatile STT-RAM technology; Random access memory;
Conference_Titel :
Device Research Conference (DRC), 2010
Conference_Location :
South Bend, IN
Print_ISBN :
978-1-4244-6562-0
Electronic_ISBN :
1548-3770
DOI :
10.1109/DRC.2010.5551946
