Title :
Fast energy aware application specific Network-on-Chip topology generator
Author :
Choudhary, Naveen ; Gaur, S.M. ; Laxmi, V. ; Singh, V.
Author_Institution :
Dept. of Comput. Eng., Malaviya Nat. Inst. of Technol., Jaipur, India
Abstract :
Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. In this paper, fast deterministic methodologies are proposed for synthesis of energy aware communication architecture along with corresponding routing tables of an application specific NoC where the traffic communication traffic characteristics can be well characterized at design time.
Keywords :
integrated circuit design; network routing; network-on-chip; NoC; energy aware communication synthesis; high-performance nanoscale architecture; network-on-chip topology generator; routing tables; traffic communication; Network topology; Network-on-a-chip; Cores; Deterministic; Energy; Network-on-Chip; Performance;
Conference_Titel :
Advance Computing Conference (IACC), 2010 IEEE 2nd International
Conference_Location :
Patiala
Print_ISBN :
978-1-4244-4790-9
Electronic_ISBN :
978-1-4244-4791-6
DOI :
10.1109/IADCC.2010.5423002
