A parallel low latency bus on chip for packet processing MPSoC

In this paper an bus architecture combining crossbar switching with split transaction feature is presented for multiprocessor system on chip (MPSoC) in the packet processing application. The high throughput is achieved with crossbar bus topology and low bus latency is finished by split transaction buses which separate address bus from data one. Experimental results show that performance of the proposed architecture is improved up to 2.3 times than the one of the AHB buses and reduce communication latency about 45% than the later. Moreover, the bus arbiter implementation has reasonable area and timing cost which make it suitable for high performance IP-packet or base-band processing.