AES implementation based on a configurable VLIW DSP

This paper presents the design and implementation of an Advanced Encryption Standard (AES) algorithm using configurable DSP processor design tools. Beginning with the NIST specification, a software algorithm is developed and then hardware implementations are profiled and tuned by adding or removing configurable computing units. Finally, RTL implementations are generated. Performance is compared to commercial implementations. The DSP exploration process allowed rapid development of increasingly better implementations of the algorithm.