DocumentCode
1629511
Title
Analysis and design of low-jitter clock driver for wideband ADC
Author
Cheng, Long ; Yang, Haifeng ; Luo, Lei ; Ren, Junyan
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear
2010
Firstpage
515
Lastpage
517
Abstract
The method of using small-signal model to analyze jitter of the clock driver caused by thermal noise is presented. Multi-stage quasi-infinite load differential amplifier structure to effectively achieve low clock jitter is proposed. With transient noise simulation, jitter in the clock driver can be calculated. Through testing the SNR of ADC, The jitter of the designed clock driver in this paper is below 260 fs so that it can be used in the high performance ADC.
Keywords
analogue-digital conversion; clocks; differential amplifiers; thermal noise; timing jitter; low-jitter clock driver; quasi-infinite load differential amplifier; small-signal model; thermal noise; transient noise simulation; wideband analog-digital conveters; Clocks; Differential amplifiers; Driver circuits; Jitter; Noise; Thermal noise; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4244-5797-7
Type
conf
DOI
10.1109/ICSICT.2010.5667355
Filename
5667355
Link To Document