DocumentCode :
1629635
Title :
A closed form delay evaluation approach using burr´s distribution function for high speed on-chip RC interconnects
Author :
Kar, R. ; Maheshwari, V. ; Maqbool, Masood ; Mal, A.K. ; Bhattacharjee, A.K.
Author_Institution :
Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Durgapur, India
fYear :
2010
Firstpage :
129
Lastpage :
133
Abstract :
As the present day technology is shrinking towards nanometer regime, interconnect delay is more dominant compared to gate delay. Hence the calculation of interconnect delay is more crucial and plays a major role for both performance and physical design optimization for high speed CMOS integrated circuits. Many approaches primarily concentrated to find the interconnect delay rather than gate delay so that one can enhance the speed of the circuit by simply decreasing interconnect length. Statistical timing analysis techniques are being developed to tackle this important problem. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. For optimizations like physical synthesis and statistical timing analysis, efficient interconnect delay computation is critical. By considering the impulse responses of linear circuit as a Probability Distribution Function (PDF), Elmore first estimated the value of interconnects delay. Several approaches have been proposed after Elmore Delay metric like, PRIMO, AWE, h-gamma etc. are proven to be more accurate than Elmore delay metric. Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (first moment of the impulse response) expression, to moment matching methods which create reduced order trans-impedance and transfer function approximations. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delay can be estimated from probability tables. The accuracy of our model is justified with the results compared with that of SPICE simulations and the models that have already being proposed with other probability distribution function.
Keywords :
CMOS integrated circuits; RC circuits; VLSI; circuit optimisation; delay estimation; delays; integrated circuit interconnections; probability; timing; transfer functions; transient response; Burr distribution function; CMOS integrated circuits; Elmore delay metric; SPICE simulation; VLSI; closed form delay evaluation; critical dimensions; gate delay; impulse response; interconnect delay; interconnect length; moment matching; on-chip RC interconnects; physical design optimization; probability distribution function; statistical timing analysis; timing verification; transfer function approximations; CMOS integrated circuits; CMOS technology; Delay estimation; Design optimization; Distribution functions; Integrated circuit interconnections; Integrated circuit technology; Probability distribution; Timing; Very large scale integration; Burr´s distribution; Delay calculation; Distribution function; Interconnec; Moment matching; VLSI;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advance Computing Conference (IACC), 2010 IEEE 2nd International
Conference_Location :
Patiala
Print_ISBN :
978-1-4244-4790-9
Electronic_ISBN :
978-1-4244-4791-6
Type :
conf
DOI :
10.1109/IADCC.2010.5423023
Filename :
5423023
Link To Document :
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