A novel VLSI BiCMOS/bipolar concurrent multiplier-accumulator for DSP applications

The authors present the design of a novel BiCMOS/bipolar concurrent multiplier-accumulator (BICMAC) architecture that can be configured on-the-fly for selecting multiply alone or multiply-accumulation (add/subtract) computations involving unsigned/signed 2´s compliment/mixed-mode data formats for normal as well as extended precision arithmetic. The proposed BICMAC does not require the use of a separate adder module normally used in the conventional MACs thereby achieving approximate reductions of 50% and 20%, respectively, in the computation time and area making it attractive for VLSI implementation. It can be used as a fundamental computing block of the algorithmically specialized integrated circuits, like, systolic and wavefront array processors for an efficient implementation of the computationally intensive DSP functions: FIR/IIR filtering, correlation, matrix multiplication, etc., resulting in reduced hardware complexity and latency. The technology independent nature of the proposed architecture makes it attractive also for VLSI implementation using fast emerging contemporary technologies: GaAs (MESFET, HEMT, JFET) and HBT