Title :
A robust multipurpose PLL with lock detector designed in a 0.35 μm CMOS technology
Author :
Gyepes, G. ; Stopjakova, V. ; Arbet, D. ; Nagy, G. ; Majer, Libor
Author_Institution :
Dept. of IC Design & Test, Slovak Univ. & Technol., Bratislava, Slovakia
Abstract :
In this paper, the design of a phase locked loop (PLL) with an additional lock detector with multiple output is presented. The proposed PLL is optimized for 2.5 V supply voltage and 20 MHz input reference signal. The PLL circuit also has 3 outputs of 170 MHz, 10.625 MHz and 10 MHz frequency. A lock detector is included in the PLL design, which indicates the lock state by generating logic 1 at its output. The complete design occupies 274 × 345 μm2.
Keywords :
CMOS integrated circuits; phase locked loops; CMOS technology; frequency 10 MHz; frequency 10.625 MHz; frequency 170 MHz; frequency 20 MHz; lock detector; multipurpose PLL; phase locked loop; size 0.35 mum; voltage 2.5 V; Charge pumps; Detectors; Flip-flops; Frequency conversion; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; charge-pump; frequency divider; phased locked loop; voltage controlled oscillator;
Conference_Titel :
Applied Electronics (AE), 2013 International Conference on
Conference_Location :
Pilsen
Print_ISBN :
978-80-261-0166-6
