Behavioral modeling of Si LDMOS pre-matched devices with application to Doherty power amplifiers

Development of an experimental behavioral model to describe the non-linear characteristics of high power internally pre-matched LDMOS power transistors is presented. The model is developed by characterizing the device with swept power load-pull measurements across a large load impedance plane with the input impedance set at a pre-determined state. Based on measurements of complex input and output voltages at the device´s package terminals, a functional representation is adopted to express the device´s complex gain with respect to RF input voltage (or available source power) and the device´s load terminating impedance. It is further shown that this approach can be used to independently model high power LDMOS pre-matched devices biased at Class-A/B and -C for use in simulating a complete Doherty power amplifier circuit. Simulations of a 300W Doherty power amplifier using this approach are contrasted to more conventional compact device models with excellent agreement noted across a large output power range. Hence, when compact models are unavailable, a behavioral one can be formulated from load pull measurements on the devices of interest.