DocumentCode
1630430
Title
Session Abstract
Author
Parekhji, R.A.
Author_Institution
Texas Instruments, Ltd., India
fYear
2006
Firstpage
86
Lastpage
87
Abstract
Large designs, larger test pattern volumes and longer test times have necessitated the use of test data and test time compression techniques built around the scan design paradigm. The adoption of these techniques is increasing. Much as well as they are understood today, these techniques continue to present challenges in their adoption and implementation. As their adoption increases, new compression targets are set, in turn forcing the investigation of better solutions and upper bounds. In this Innovative Practices track session, implementation case studies for various scan compression techniques will be presented, together with their tradeoffs and entitlement. Emerging developments in these technologies will be described, together with some theoretical results and possibilities.
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Print_ISBN
0-7695-2514-8
Type
conf
DOI
10.1109/VTS.2006.78
Filename
1617567
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