Title :
Interconnect testing for networks on chips
Author :
Stewart, Khadija ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A scheme to functionally test the networking infrastructure of a system within a network on chip is presented. A fault model and a test pattern generation and application algorithm that relies on a network simulator are presented. Experimental results demonstrate the impact of the presented algorithm.
Keywords :
integrated circuit interconnections; integrated circuit testing; network-on-chip; application algorithm; interconnect testing; network simulator; networking infrastructure; networks on chips; test pattern generation; Circuit faults; Computer architecture; Computer networks; Delay; Integrated circuit interconnections; Master-slave; Network interfaces; Network-on-a-chip; System testing; System-on-a-chip;
Conference_Titel :
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Print_ISBN :
0-7695-2514-8
DOI :
10.1109/VTS.2006.41
