Area optimization algorithm for body-bias based on input vector control

With the technology scaling down to the deep sub-micron domain, leakage power increases rapidly in VLSI, enhancing the area overhead of dynamic power management system. Reverse Body Bias(RBB) is a common method to reduce the leakage power at run-time. To overcome the larger area overhead of controller applied on RBB, this paper proposes a new way of connection, which can reduce area of controller substantially. Based on dual-threshold voltage CMOS designs, when the input vector is the minimum leakage pattern, this paper applies VRBB to the low threshold voltage (LVT) and Dominate Leakage State (DLS) MOS transistors. Experimental results is based on a set of ISCAS85 benchmark circuits in a Predictive 22 nm process, comparing with previous works, this algorithm can reduce 84.91% area overhead with the cost of 27.94% leakage current penalty.