Title :
An integrated analog test simulation environment
Author :
Webster, Bruce A.
Author_Institution :
Teradyne Inc., Boston, MA, USA
Abstract :
An integrated test simulation environment which links circuit simulation data and tester simulation is presented. This environment is critical to the computer-aided development of test packages for analog integrated circuits. A working example is presented. The overall benefit of the integrated simulation environment described is a shortening of the test development cycle. By allowing the test engineer to begin test package development earlier, the overall, IC design/test process shifts from a serial task to one with significant overlap
Keywords :
analogue circuits; automatic testing; circuit CAD; integrated circuit testing; linear integrated circuits; IC design/test; analog integrated circuits; circuit CAD; circuit simulation; computer-aided development; integrated analog test simulation environment; tester simulation; Analog computers; Circuit simulation; Circuit testing; Computational modeling; Hardware; Instruments; Logic testing; Performance evaluation; Software testing; Voltage;
Conference_Titel :
Test Conference, 1989. Proceedings. Meeting the Tests of Time., International
Conference_Location :
Washington, DC
DOI :
10.1109/TEST.1989.82341
