Improved handling of false and multicycle paths in ATPG

As electronic design feature sizes continue to shrink and clock speeds continue to rise, more and more companies have turned to at-speed test techniques to help ensure high test and product quality. An important piece of the design flow is static timing analysis (STA), which is used to verify the timing of paths in the design. Part of the STA process is to specify false and multicycle path exceptions to relax the timing for these paths for synthesis and layout purposes. This paper explains the importance of using these timing path exceptions during automatic test pattern generation (ATPG) and compares previous methods of handling these paths to a new innovative method that provides higher test and product quality