Title :
A design methodology of bipolar standard cell LSIs for Gbit/s signal processing
Author :
Koike, Keiichi ; Kawai, Kenji ; Ichino, Haruhiko
Author_Institution :
NTT LSI Lab., Kanagawa, Japan
Abstract :
A bipolar standard cell LSI design methodology for Gbit/s LSIs is described. A unique configuration of cell libraries which have internal fixed routing channels especially for differential clocks and a clock distribution scheme that considers the equal length and load of differential clocks makes it possible to achieve a 1.8 Gbit/s 2.5 K-gate LSI
Keywords :
very high speed integrated circuits; 1.8 Gbit/s; bipolar standard cell LSIs; cell libraries; clock distribution scheme; design methodology; differential clocks; internal fixed routing channels; very high speed; Very-high-speed integrated circuits;
Conference_Titel :
Bipolar/BiCOMS Circuits and Technology Meeting, 1993., Proceedings of the 1993
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-1316-X
DOI :
10.1109/BIPOL.1993.617506
