Title :
Design optimization for robustness to single-event upsets
Author :
Zhou, Quming ; Choudhury, Mihir R. ; Mohanram, Kartik
Author_Institution :
Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX
Abstract :
An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model is integrated with area and performance constraints into an optimization framework based on geometric programming for design space exploration. Simulation results demonstrate the design tradeoffs that can be achieved with this approach
Keywords :
circuit optimisation; circuit simulation; combinational circuits; geometric programming; logic gates; SEU robustness; combinational circuits; design space exploration; geometric programming; logic gate; optimization algorithm; single-event upsets; Algorithm design and analysis; Combinational circuits; Constraint optimization; Design optimization; Logic gates; Logic programming; Robustness; Single event transient; Single event upset; Solid modeling;
Conference_Titel :
VLSI Test Symposium, 2006. Proceedings. 24th IEEE
Conference_Location :
Berkeley, CA
Print_ISBN :
0-7695-2514-8
DOI :
10.1109/VTS.2006.28
